This invention generally relates to measuring timing characteristics of SRAM chips; and more specifically, the invention relates to timing measurements of data-pins spread and access times for such chips.
Traditionally, at-speed component test has guaranteed all AC timing specifications for SRAMs. The performance of high-speed SRAMs is presently limited, however, by tester accuracy in the measurement of input/output (I/O) timings. Specifically, access-time measurements, I/O pin-to-pin skew measurements, and echo-clock-to-data tracking measurements may only be externally determined to an accuracy of +/-200 ps or more. This external limitation can result in high-performance components becoming unnecessarily downgraded to lower performance applications. This downgrading results in a substantial reduction in high-performance applications and in a substantial reduction in high-performance product yield. In addition, the need for ever-increasing tester accuracy causes high test-equipment and manufacturing test costs.
For example, a device being tested for an access time of 1.5 ns will be subject to two external test constraints. First, the tester guardband is subtracted from the access-time strobe. For a typical high-speed tester, this guardband is 200 ps. Second, the access-time measurement is referenced to the worst-case (i.e., slowest) I/O of the chip. A 200 ps tester-induced pin-to-pin I/O spread results in an additional access time penalty because the access strobe must capture the slowest pin of the spread. In contrast to this wide spread induced by the tester, the pin-to-pin spread intrinsic to the SRAM can be as narrow as 30 ps for a well-matched design. A combined tester-imposed penalty of 300 ps from these two constraints requires that a device have an intrinsic access time of approximately 1.2 ns to meet a 1.5 ns specification at test. The same constraints apply for measurements of echo-clock to data tracking.